This application claims the priority benefit of Taiwan application serial no. 90106035, filed Mar. 15, 2001.
1. Field of Invention
The present invention relates to a type of flash memory. More particularly, the present invention relates to a flash memory having an erasing device for erasing all data within a plurality of memory blocks at the same time.
2. Description of Related Art
In U.S. Pat. No. 5,978,275 with the title xe2x80x9cErase and Program Control State Machines for Flash Memoryxe2x80x9d, an erase state machine is used to control the erasure of data within specified memory blocks. Thereafter, the memory blocks are checked to ascertain the complete erasure of data from memory.
Although the conventional technique can delete the data within specified memory blocks of a flash memory on command, a large number of complicated electronic circuit devices is employed, leading to a complex routing circuit and a big increase in production cost.
Accordingly, one object of the present invention is to provide an erase device for a flash memory that not only can simplify circuit layout and reduce production cost, but can also simultaneously erase a variable number of memory blocks.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides an erase device and a method of erasing data from a flash memory. The erase device includes a shift control signal transmission terminal, an erase control group and a pulse control group. The shift control signal transmission terminal is used for transmitting a shift control signal. The erase control group includes a plurality of serially connected erase controllers. Each erase controller corresponds to a memory block. Each of the erase controllers contains a shift register, a receiving terminal and an output terminal. The receiving terminal of the first erase controller receives a shift control signal sent from the shift control signal transmission terminal. The receiving terminal of a subsequent erase controller connects electrically with the output terminal of the previous erase controller. In addition, the shift register contains a shift control signal received from the receiving terminal. The shift control signal is used for directing the erasure of memory block data that correspond to the erase controller. The pulse control signal group controls the sending and the receiving of shift control signals.
This invention also provides a method of erasing flash memory data related to the erasing operation. The flash memory includes a plurality of memory blocks with each memory block having a corresponding erase controller.
The method of erasing flash memory includes the following steps. First, the memory blocks from which data needs to be erased are set. These memory blocks are set by transmitting an erase signal to a latching register within the corresponding erase controllers. Thereafter, a preset number of pulses related to the pulse control signal are produced. According to the pulse control signal, shift control signals are sequentially transferred to the serially connected erase controller. Finally, according to the shift control signal and the erase signal, the erase controller erases the content within the memory blocks.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.